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Single-Phase PWM Regulator for IMVP-6.5TM Mobile CPUs and GPUs
ISL62881, ISL62881B
The ISL62881 is a single-phase PWM buck regulator for miroprocessor or graphics processor core power supply. It uses an integrated gate drivers to provide a complete solution. The PWM modulator of ISL62881 is based on Intersil's Robust Ripple Regulator (R3) technologyTM. Compared with traditional modulators, the R3TM modulator commands variable switching frequency during load transients, achieving faster transient response. With the same modulator, the switching frequency is reduced at light load, increasing the regulator efficiency. The ISL62881 can be configured as CPU or graphics Vcore controller and is fully compliant with IMVP-6.5TM specifications. It responds to DPRSLPVR signals by entering/exiting diode emulation mode. It reports the regulator output current through the IMON pin. It senses the current by using either discrete resistor or inductor DCR whose variation over-temperature can be thermally compensated by a single NTC thermistor. It uses differential remote voltage sensing to accurately regulate the processor die voltage. The adaptive body diode conduction time reduction function minimizes the body diode conduction loss in diode emulation mode. User-selectable overshoot reduction function offers an option to aggressively reduce the output capacitors as well as the option to disable it for users concerned about increased system thermal stress. Maintaining all the ISL62881 functions, the ISL62881B offers VR_TT# function for thermal throttling control. It also offers the split LGATE function to further improve light load efficiency.
ISL62881, ISL62881B
Features
* Precision Core Voltage Regulation - 0.5% System Accuracy Over-Temperature - Enhanced Load Line Accuracy * Voltage Identification Input - 7-Bit VID Input, 0V to 1.500V in 12.5mV Steps - Supports VID Changes On-The-Fly * Supports Multiple Current Sensing Methods - Lossless Inductor DCR Current Sensing - Precision Resistor Current Sensing * Superior Noise Immunity and Transient Response * Current Monitor * Differential Remote Voltage Sensing * High Efficiency Across Entire Load Range * Integrated Gate Driver * Split LGATE Driver to Increase Light-Load Efficiency (For ISL62881B) * Adaptive Body Diode Conduction Time Reduction * User-selectable Overshoot Reduction Function * Capable of Disabling the Droop Function * Audio-filtering for GPU Application * Small Footprint 28 Ld 4x4 TQFN Package * Pb-Free (RoHS Compliant)
Applications
* Notebook Computers
Ordering Information
PART NUMBER (Notes 1, 2, 3) ISL62881HRTZ ISL62881BHRTZ NOTES: 1. Add "-T" suffix for tape and reel. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see device information page for ISL62881, ISL62881B. For more information on MSL please see techbrief TB363. PART MARKING 628 81HRTZ 62881B HRTZ TEMP. RANGE (C) -10 to +100 -10 to +100 PACKAGE (Pb-Free) 28 Ld 4x4 TQFN 32 Ld 5x5 TQFN PKG. DWG. # L28.4x4 L32.5x5E
February 25, 2010 FN6924.1
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CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2009, 2010. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ISL62881, ISL62881B
Pin Configurations
ISL62881 (28 LD TQFN) TOP VIEW
DPRSLPVR
ISL62881B (32 LD TQFN) TOP VIEW
DPRSLPVR CLK_EN# VR_ON
VR_ON
VID3
VID4
VID2
VID6
VID5
VID4
VID6
VID5
VID3
28 27 26 25 24 23 22 CLK_EN# 1 PGOOD 2 RBIAS 3 VW 4 GND PAD (BOTTOM) 21 VID1 20 VID0 19 VCCP 18 LGATE 17 VSSP 16 PHASE 15 UGATE 8 RTN 9 ISUM10 11 12 13 14 VIN IMON ISUM+ BOOT VDD PGOOD 1 RBIAS 2 VR_TT# 3 NTC 4 GND 5 VW 6 COMP 7 FB 8
32 31 30 29 28 27 26 25 24 VID1 23 VID0 22 VCCP GND PAD (BOTTOM) 21 LGATEb 20 LGATEa 19 VSSP 18 PHASE 17 UGATE 9 10 11 12 13 14 15 16 VIN ISUMISUM+ IMON BOOT
FN6924.1 February 25, 2010
COMP 5 FB 6
VSEN 7
VSEN
RTN
Pin Function Description
GND (Bottom Pad)
Signal common of the IC. Unless otherwise stated, signals are referenced to the GND pin.
COMP
This pin is the output of the error amplifier. Also, a resistor across this pin and GND adjusts the overcurrent threshold.
CLK_EN#
Open drain output to enable system PLL clock; goes active 13 switching cycles after Vcore is within 10% of Vboot.
FB
This pin is the inverting input of the error amplifier.
VSEN
Remote core voltage sense input. Connect to microprocessor die.
PGOOD
Power-Good open-drain output indicating when the regulator is able to supply regulated voltage. Pull-up externally with a 680 resistor to VCCP or 1.9k to 3.3V.
RTN
Remote voltage sensing return. Connect to ground at microprocessor die.
RBIAS
A resistor to GND sets internal current reference. A 147k resistor sets the controller for CPU core application and a 47k resistor sets the controller for GPU core application.
ISUM- and ISUM+
Droop current sense input.
VDD
5V bias power.
VR_TT#
Thermal overload output indicator.
VIN
Battery supply voltage, used for feed-forward.
NTC
Thermistor input to VR_TT# circuit.
IMON
An analog output. IMON outputs a current proportional to the regulator output current.
VW
A resistor from this pin to COMP programs the switching frequency (8k gives approximately 300kHz).
BOOT
Connect an MLCC capacitor across the BOOT and the PHASE pins. The boot capacitor is charged through an internal boot diode connected from the VCCP pin to the BOOT pin, each time the PHASE pin drops below VCCP
2
VDD
VID2
ISL62881, ISL62881B
minus the voltage dropped across the internal boot diode.
UGATE
Output of the high-side MOSFET gate driver. Connect the UGATE pin to the gate of the high-side MOSFET.
PHASE
Current return path for the high-side MOSFET gate driver. Connect the PHASE pin to the node consisting of the high-side MOSFET source, the low-side MOSFET drain and the output inductor.
VSSP
Current return path for the low-side MOSFET gate driver. Connect the VSSP pin to the source of the low-side MOSFET through a low impedance path, preferably in parallel with the trace connecting the LGATE pin to the gate of the low-side MOSFET.
LGATE (For ISL62881)
Output of the low-side MOSFET gate driver. Connect the LGATE pin to the gate of the low-side MOSFET.
LGATEa (For ISL62881B)
Output of the low-side MOSFET gate driver that is always active. Connect the LGATEa pin to the gate of the lowside MOSFET that is active all the time.
LGATEb (For ISL62881B)
Another output of the low-side MOSFET gate driver. This gate driver will be pulled low when the DPRSLPVR pin logic is high. Connect the LGATEb pin to the gate of the low-side MOSFET that is idle in deeper sleep mode.
VCCP
Input voltage bias for the internal gate drivers. Connect +5V to the VCCP pin. Decouple with at least 1F of an MLCC capacitor to VSSP1 and VSSP2 pins respectively.
VID0, VID1, VID2, VID3, VID4, VID5, VID6
VID input with VID0 = LSB and VID6 = MSB.
VR_ON
Voltage regulator enable input. A high level logic signal on this pin enables the regulator.
DPRSLPVR
A high level logic signal on this pin puts the ISL62881 in 1-phase diode emulation mode. If RBIAS = 47k (GPU VR application), this pin also controls Vcore slew rate. Vcore slews at 5mV/s for DPRSLPVR = 0 and 10mV/s for DPRSLPVR = 1. If RBIAS = 147k (CPU VR application), this pin doesn't control Vcore slew rate.
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ISL62881, ISL62881B
Block Diagram
VIN VSEN PGOOD CLK_EN# VDD
VR_ON MODE CONTROL DPRSLPVR RBIAS PROTECTION VID0 VID1 VID2 VID3 VID4 VID5 DAC AND SOFT START VIN WOC OC CLOCK VDAC COMP VW PGOOD AND CLK_EN# LOGIC FLT
6A 54A 1.20V 1.24V
VR_TT#
NTC
ISL62881B ONLY
PWM CONTROL LOGIC
VID6 RTN FB COMP VW Idroop Imon IMON ISUM+ ISUMCURRENT SENSE 2.5 X WOC VIN VDAC
BOOT
DRIVER
UGATE PHASE
E/A
SHOOT THROUGH PROTECTION DRIVER
VCCP LGATEA VSSP ISL62881 ONLY
MODULATOR COMP
CURRENT 60A COMPARATORS OC
DRIVER
LGATEB ISL62881B ONLY GND
ADJ. OCP THRESHOLD
COMP
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Absolute Maximum Ratings
Supply Voltage, VDD. . . . . . . . . . . . . . . . . . . .-0.3V to +7V Battery Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . . +28V Boot Voltage (BOOT) . . . . . . . . . . . . . . . . . . -0.3V to +33V Boot to Phase Voltage (BOOT-PHASE) . . . . -0.3V to +7V(DC) . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +9V(<10ns) Phase Voltage (PHASE) . . . . . -7V (<20ns Pulse Width, 10J) UGATE Voltage (UGATE) . . . . . . . PHASE-0.3V (DC) to BOOT . . . . . . . . . PHASE-5V (<20ns Pulse Width, 10J) to BOOT LGATE Voltage (LGATE) . . . . . . . . -0.3V (DC) to VDD + 0.3V . . . . . . . . . -2.5V (<20ns Pulse Width, 5J) to VDD + 0.3V All Other Pins. . . . . . . . . . . . . . . . . . -0.3V to (VDD + 0.3V) Open Drain Outputs, PGOOD, VR_TT#, CLK_EN# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +7V
Thermal Information
Thermal Resistance (Typical, Notes 4, 5)JA (C/W) JC (C/W) 28 Ld TQFN Package. . . . . . . . . . . 40 3 32 Ld TQFN Package. . . . . . . . . . . 32 3 Maximum Junction Temperature . . . . . . . . . . . . . . . +150C Maximum Storage Temperature Range . . . -65C to +150C Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Supply Voltage, VDD . Battery Voltage, VIN . Ambient Temperature Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V 5% . . . +4.5V to 25V -10C to +100C -10C to +125C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.
NOTES: 4. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with "direct attach" features. See Tech Brief TB379. 5. For JC, the "case temp" location is the center of the exposed metal pad on the package underside.
Electrical Specifications
Operating Conditions: VDD = 5V, TA = -10C to +100C, fSW = 300kHz, unless otherwise noted. Boldface limits apply over the operating temperature range, -10C to +100C. SYMBOL IVDD IVIN RVIN PORr PORf TEST CONDITIONS VR_ON = 1V VR_ON = 0V VR_ON = 0V VR_ON = 1V VDD rising VDD falling 4.00 -0.5 -8 -15 1.0945 1.100 1.500 0 1.45 295 200 IFB = 0A Av0 GBW CL = 20pF -0.15 90 18 1.47 310 1.49 325 500 +0.15 900 4.35 4.15 +0.5 +8 +15 1.1055 4.5 MIN MAX (Note 7) TYP (Note 7) UNITS 3.2 4.0 1 1 mA A A k V V % mV mV V V V V kHz kHz mV dB MHz
PARAMETER INPUT POWER SUPPLY +5V Supply Current Battery Supply Current VIN Input Resistance Power-On-Reset Threshold SYSTEM AND REFERENCES System Accuracy
%Error (VCC_CORE) No load; closed loop, active mode range VID = 0.75V to 1.50V VID = 0.5V to 0.7375V VID = 0.3V to 0.4875V
VBOOT Maximum Output Voltage Minimum Output Voltage (Note 6) RBIAS Voltage CHANNEL FREQUENCY Nominal Channel Frequency Adjustment Range AMPLIFIERS Current-Sense Amplifier Input Offset Error Amp DC Gain (Note 6) Error Amp Gain-Bandwidth Product (Note 6) fSW(nom) RFSET = 7k, VCOMP = 1V VCC_CORE(max) VCC_CORE(min) VID = [0000000] VID = [1111111] RBIAS = 147k
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ISL62881, ISL62881B
Electrical Specifications
Operating Conditions: VDD = 5V, TA = -10C to +100C, fSW = 300kHz, unless otherwise noted. Boldface limits apply over the operating temperature range, -10C to +100C. (Continued) SYMBOL VOL IOH tpgd RUGPU IUGSRC RUGPD IUGSNK RLGPU ILGSRC RLGPD ILGSNK tUGFLGR tLGFUGR RLGPU ILGSRC RLGPD ILGSNK tUGFLGR tLGFUGR TEST CONDITIONS IPGOOD = 4mA PGOOD = 3.3V CLK_ENABLE# LOW to PGOOD HIGH 200mA Source Current BOOT - UGATE = 2.5V 250mA Sink Current UGATE - PHASE = 2.5V 250mA Source Current VCCP - LGATE = 2.5V 250mA Sink Current LGATE - VSSP = 2.5V UGATE falling to LGATE rising, no load LGATE falling to UGATE rising, no load 250mA Source Current VCCP - LGATEa and b = 2.5V 250mA Sink Current LGATEa and b - VSSP = 2.5V UGATE falling to LGATEa and b rising, no load LGATEa and b falling to UGATE rising, no load PVCC = 5V, IF = 2mA VR = 25V VSEN rising above setpoint for >1ms VSEN rising for >2s ISUM- pin current UVf VIL(1.0V) VSEN falling below setpoint for >1.2ms 150 1.525 8.2 -355 -1 6.3 7.6 MIN MAX (Note 7) TYP (Note 7) UNITS 0.26 0.4 1 8.9 V A ms
PARAMETER PGOOD Low Voltage PGOOD Leakage Current PGOOD Delay UGATE DRIVER UGATE Pull-Up Resistance (Note 6) UGATE Source Current (Note 6) UGATE Sink Resistance (Note 6) UGATE Sink Current (Note 6) LGATE DRIVER For ISL62881 LGATE Pull-Up Resistance (Note 6) LGATE Source Current (Note 6) LGATE Sink Resistance (Note 6) LGATE Sink Current (Note 6) UGATE to LGATE Deadtime LGATE to UGATE Deadtime LGATEa and b Pull-Up Resistance (Note 6) LGATEa and b Source Current (Note 6) LGATEa and b Sink Resistance (Note 6) LGATEa and b Sink Current (Note 6) UGATE to LGATEa and b Deadtime LGATEa and b to UGATE Deadtime BOOTSTRAP DIODE Forward Voltage Reverse Leakage PROTECTION Overvoltage Threshold Severe Overvoltage Threshold OC Threshold Offset Undervoltage Threshold LOGIC THRESHOLDS VR_ON Input Low
POWER GOOD AND PROTECTION MONITORS
1.0 2.0 1.0 2.0
1.5
A
1.5
A
1.0 2.0 0.5 4.0 23 28
1.5
A
0.9
A ns ns
LGATE DRIVERS For ISL62881B 2.0 1.0 1 2.0 23 28 1.8 3 A A ns ns
VF IR OVH OVHS
0.58 0.2 200 1.55 10.1 -295 240 1.575 12 -235 0.3
V A mV V A mV V
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FN6924.1 February 25, 2010
ISL62881, ISL62881B
Electrical Specifications
Operating Conditions: VDD = 5V, TA = -10C to +100C, fSW = 300kHz, unless otherwise noted. Boldface limits apply over the operating temperature range, -10C to +100C. (Continued) SYMBOL VIH(1.0V) VIL(1.0V) VIH(1.0V) 0.7 TEST CONDITIONS MIN MAX (Note 7) TYP (Note 7) UNITS 0.7 0.3 V V V
PARAMETER VR_ON Input High VID0-VID6 and DPRSLPVR Input Low VID0-VID6 and DPRSLPVR Input High NTC Source Current Over-Temperature Threshold VR_TT# Low Output Resistance CLK_EN# OUTPUT LEVELS CLK_EN# Low Output Voltage CLK_EN# Leakage Current CURRENT MONITOR IMON Output Current
THERMAL MONITOR (For ISL62881B) NTC = 1.3V V (NTC) falling RTT I = 20mA 53 1.18 60 1.2 6.5 67 1.22 9 A V
VOL IOH IIMON
I = 4mA CLK_EN# = 3.3V ISUM- pin current = 20A ISUM- pin current = 10A ISUM- pin current = 5A -1 108 51 22
0.26
0.4 1
V A A
120 60 30 1.1 275
132 69 37.5 1.15
IMON Clamp Voltage Current Sinking Capability INPUTS VR_ON Leakage Current VIDx Leakage Current DPRSLPVR Leakage Current SLEW RATE Slew Rate (For VID Change) NOTES:
VIMONCLAMP
V A A
IVR_ON IVIDx IDPRSLPVR
VR_ON = 0V VR_ON = 1V VIDx = 0V VIDx = 1V DPRSLPVR = 0V DPRSLPVR = 1V
-1 -1 -1
0 0 0 0.45 0 0.45 1 6.5 1 1
A A A A A mV/s
SR
5
6. Limits established by characterization and are not production tested. 7. Parameters with MIN and/or MAX limits are 100% tested at +25C, unless otherwise specified. Temperature limits established by characterization and are not production tested.
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FN6924.1 February 25, 2010
ISL62881, ISL62881B
Gate Driver Timing Diagram
PWM
tLGFUGR
tRU 1V
tFU
UGATE
LGATE tFL
1V tRL
tUGFLGR
Simplified Application Circuits
V+5 V+5 V IN V IN
R B IA S
VDD VCCP R B IA S
PGOOD C LK _E N # V ID < 0:6 > D P R S LP V R V R _O N
PGOOD C LK _E N # V ID S D P R S LP V R VR_ON VW
RFSET
IS L 6 2 8 8 1 BOOT UGATE PHASE V IN L VO
COM P FB R DROOP VSEN
LG A T E VSSP
R SUM
IS U M + RIS RTN R IM O N IM O N IM O N IS U M (B O T T O M P A D ) VSS CIS RI CN C RN
V C C S EN S E V S S S EN S E
FIGURE 1. ISL62881 TYPICAL APPLICATION CIRCUIT USING DCR SENSING
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Simplified Application Circuits (Continued)
V+5 V+5 VIN R BIAS VDD VCCP VIN RBIAS PGOOD CLK_EN# VID<0:6> DPRSLPVR VR_ON PGOOD CLK_EN# VIDS DPRSLPVR VR_ON VW RFSET ISL62881 BOOT UGATE PHASE COMP FB R DROOP VSEN ISUM+ RIS RTN R IMON IMON ISUMIMON (BOTTOM PAD) VSS CIS RI CN R SUM LGATE VSSP VIN L RSEN VO
VCC SENSE VSS SENSE
FIGURE 2. ISL62881 TYPICAL APPLICATION CIRCUIT USING RESISTOR SENSING
V+5 R B IA S V+5 V IN V IN
V DD V CCP R B IA S N TC V R _ TT # PGOOD C LK _ E N # V ID S D P R S LP V R VR_ON VW
OC VR_TT# PGOOD CLK_EN# V ID < 0 :6 > D P R S LP V R VR_ON
IS L 6 2 8 8 1 B
BOOT V IN L VO
RFSET
UGATE CO M P FB PHASE LG A T E B LG A TE A VSSP
RSUM
R DROOP V SE N IS U M + RIS RTN R IM O N IM O N IM O N ISU M GND CIS RI CN RN
V C C S EN S E V S S S EN S E
OC
FIGURE 3. ISL62881B TYPICAL APPLICATION CIRCUIT USING DCR SENSING
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Simplified Application Circuits (Continued)
V+5 R BIAS V+5 V IN V IN V DD VCCP R BIAS NTC VR_TT# PGOOD CLK_EN# VIDS DPRSLPVR VR_ON VW ISL62881B BOOT RFSET UGATE COMP FB R DROOP VSEN ISUM+ RIS RTN R IMON IMON IMON VSS ISUMCIS RI CN RSUM PHASE LGATEB LGATEA VSSP V IN L RSEN VO
OC VR_TT# PGOOD CLK_EN# VID<0:6> DPRSLPVR VR_ON
VCCSENSE VSS SENSE
FIGURE 4. ISL62881B TYPICAL APPLICATION CIRCUIT USING RESISTOR SENSING
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Theory of Operation
Multiphase R3TM Modulator
VW MASTER CLOCK GMVO COMP VCRM CRM SLAVE CIRCUIT VW CLOCK S PWM Q R PHASE L IL VO CO MASTER CLOCK CIRCUIT CLOCK
The ISL62881 is a single-phase regulator implementing Intel(R) IMVP-6.5TM protocol. It uses Intersil patented R3TM(Robust Ripple RegulatorTM) modulator. The R3TM modulator combines the best features of fixed frequency PWM and hysteretic PWM while eliminating many of their shortcomings. Figure 5 conceptually shows the ISL62881 R3TM modulator circuit, and Figure 6 shows the operation principles. A current source flows from the VW pin to the COMP pin, creating a voltage window set by the resistor between between the two pins. This voltage window is called VW window in the following discussion. Inside the IC, the modulator uses the master clock circuit to generate the clocks for the slave circuit. The modulator discharges the ripple capacitor Crm with a current source equal to gmVo, where gm is a gain factor. Crm voltage Vcrm is a sawtooth waveform traversing between the VW and COMP voltages. It resets to VW when it hits COMP, and generates a one-shot clock signal. The slave circuit has its own ripple capacitor Crs, whose voltage mimics the inductor ripple current. A gm amplifier converts the inductor voltage into a current source to charge and discharge Crs. The slave circuit turns on its PWM pulse upon receiving the clock signal, and the current source charges Crs. When Crs voltage VCrs hits VW, the slave circuit turns off the PWM pulse, and the current source discharges Crs. Since the ISL62881 works with Vcrs, which is largeamplitude and noise-free synthesized signal, the ISL62881 achieves lower phase jitter than conventional hysteretic mode and fixed PWM mode controllers. Unlike conventional hysteretic mode converters, the ISL62881 has an error amplifier that allows the controller to maintain a 0.5% output voltage accuracy. Figure 7 shows the operation principles during load insertion response. The COMP voltage rises during load insertion, generating the clock signal more quickly, so the PWM pulse turns on earlier, increasing the effective switching frequency, which allows for higher control loop bandwidth than conventional fixed frequency PWM controllers. The VW voltage rises as the COMP voltage rises, making the PWM pulse wider. During load release response, the COMP voltage falls. It takes the master clock circuit longer to generate the next clock signal so the PWM pulse is held off until needed. The VW voltage falls as the VW voltage falls, reducing the current PWM pulse width. This kind of behavior gives the ISL62881 excellent response speed.
VCRS CRS
GM
FIGURE 5. R3TM MODULATOR CIRCUIT
VW VCRM COM P H Y S T E R E T IC W IN D O W
C LO C K PW M VW VCRS
FIGURE 6. R3TM MODULATOR OPERATION PRINCIPLES IN STEADY STATE
VW
COMP VCRM
CLOCK PWM VW
VCRS
FIGURE 7. R3TM MODULATOR OPERATION PRINCIPLES IN LOAD INSERTION RESPONSE
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ISL62881, ISL62881B
Diode Emulation and Period Stretching
VDD VR_ON
PHASE
5mV/s 2.5mV/s VBOOT 90% 800s VID COMMAND VOLTAGE
UGATE
DAC 13 SWITCHING CYCLES
LGATE
CLK_EN#
IL
PGOOD
~7ms
FIGURE 8. DIODE EMULATION
FIGURE 10. SOFT-START WAVEFORMS FOR CPU VR APPLICATION
ISL62881 can operate in diode emulation (DE) mode to improve light load efficiency. In DE mode, the low-side MOSFET conducts when the current is flowing from source to drain and doesn't not allow reverse current, emulating a diode. As shown in Figure 8, when LGATE is on, the low-side MOSFET carries current, creating negative voltage on the phase node due to the voltage drop across the ON-resistance. The ISL62881 monitors the current through monitoring the phase node voltage. It turns off LGATE when the phase node voltage reaches zero to prevent the inductor current from reversing the direction and creating unnecessary power loss. If the load current is light enough, as Figure 9 shows, the inductor current will reach and stay at zero before the next phase node pulse, and the regulator is in discontinuous conduction mode (DCM). If the load current is heavy enough, the inductor current will never reach 0A, and the regulator is in CCM although the controller is in DE mode.
CCM/DCM BOUNDARY VW VCRS
VDD VR_ON 5mV/s 90% 120s DAC 13 SWITCHING CYCLES CLK_EN# PGOOD ~7ms VID COMMAND VOLTAGE
FIGURE 11. SOFT-START WAVEFORMS FOR GPU VR APPLICATION
IL VW VCRS LIGHT DCM
Figure 9 shows the operation principle in diode emulation mode at light load. The load gets incrementally lighter in the three cases from top to bottom. The PWM on-time is determined by the VW window size, therefore is the same, making the inductor current triangle the same in the three cases. The ISL62881 clamps the ripple capacitor voltage Vcrs in DE mode to make it mimic the inductor current. It takes the COMP voltage longer to hit Vcrs, naturally stretching the switching period. The inductor current triangles move further apart from each other such that the inductor current average value is equal to the load current. The reduced switching frequency helps increase light load efficiency.
Start-up Timing
IL VW VCRS DEEP DCM
With the controller's VDD voltage above the POR threshold, the start-up sequence begins when VR_ON exceeds the 3.3V logic high threshold. Figure 10 shows the typical start-up timing when the ISL62881 is configured for CPU VR application. The ISL62881 uses digital soft-start to ramp up DAC to the boot voltage of 1.1V at about 2.5mV/s. Once the output voltage is within 10% of the boot voltage for 13 PWM cycles (43s for frequency = 300kHz), CLK_EN# is pulled low and DAC slews at 5mV/s to the voltage set by the VID pins. PGOOD is asserted high in approximately 7ms. Similar results occur if VR_ON is tied
IL
FIGURE 9. PERIOD STRETCHING
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ISL62881, ISL62881B
to VDD, with the soft-start sequence starting 120s after VDD crosses the POR threshold. Figure 11 shows the typical start-up timing when the ISL62881 is configured for GPU VR application. The ISL62881 uses digital soft-start to ramp-up DAC to the voltage set by the VID pins at 5mV/s. Once the output voltage is within 10% of the target voltage for 13 PWM cycles (43s for frequency = 300kHz), CLK_EN# is pulled low. PGOOD is asserted high in approximately 7ms. Similar results occur if VR_ON is tied to VDD, with the soft-start sequence starting 120s after VDD crosses the POR threshold.
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VO (V) 1.5000 1.4875 1.4750 1.4625 1.4500 1.4375 1.4250 1.4125 1.4000 1.3875 1.3750 1.3625 1.3500 1.3375 1.3250 1.3125 1.3000 1.2875 1.2750 1.2625 1.2500 1.2375 1.2250 1.2125 1.2000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 TABLE 1. VID TABLE (Continued) VID6 VID5 VID4 VID3 VID2 VID1 VID0 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 VO (V) 1.1875 1.1750 1.1625 1.1500 1.1375 1.1250 1.1125 1.1000 1.0875 1.0750 1.0625 1.0500 1.0375 1.0250 1.0125 1.0000 0.9875 0.9750 0.9625 0.9500 0.9375 0.9250 0.9125 0.9000 0.8875 0.8750 0.8625 0.8500 0.8375 0.8250 0.8125 0.8000 0.7875 0.7750 0.7625 0.7500 0.7375 0.7250 0.7125 0.7000 0.6875 0.6750
Voltage Regulation and Load Line Implementation
After the start sequence, the ISL62881 regulates the output voltage to the value set by the VID inputs per Table 1. The ISL62881 will control the no-load output voltage to an accuracy of 0.5% over the range of 0.75V to 1.5V. A differential amplifier allows voltage sensing for precise voltage regulation at the microprocessor die.
TABLE 1. VID TABLE VID6 VID5 VID4 VID3 VID2 VID1 VID0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
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TABLE 1. VID TABLE (Continued) VID6 VID5 VID4 VID3 VID2 VID1 VID0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 VO (V) 0.6625 0.6500 0.6375 0.6250 0.6125 0.6000 0.5875 0.5750 0.5625 0.5500 0.5375 0.5250 0.5125 0.5000 0.4875 0.4750 0.4625 0.4500 0.4375 0.4250 0.4125 0.4000 0.3875 0.3750 0.3625 0.3500 0.3375 0.3250 0.3125 0.3000 0.2875 0.2750 0.2625 0.2500 0.2375 0.2250 0.2125 0.2000 0.1875 0.1750
INTERNAL TO IC X1 COMP E/A FB R DROOP VCC SENSE VDROOP VR LOCAL VO "CATCH" RESISTOR VIDS VDAC DAC RTN VSS "CATCH" RESISTOR
TABLE 1. VID TABLE (Continued) VID6 VID5 VID4 VID3 VID2 VID1 VID0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 VO (V) 0.1625 0.1500 0.1375 0.1250 0.1125 0.1000 0.0875 0.0750 0.0625 0.0500 0.0375 0.0250 0.0125 0.0000 0.0000 0.0000 0.0000 0.0000 0.0000 0.0000 0.0000
IDROOP
VID<0:6>
VSSSENSE
FIGURE 12. DIFFERENTIAL SENSING AND LOAD LINE IMPLEMENTATION
As the load current increases from zero, the output voltage will droop from the VID table value by an amount proportional to the load current to achieve the load line. The ISL62881 can sense the inductor current through the intrinsic DC Resistance (DCR) resistance of the inductors as shown in Figure 1 or through resistors in series with the inductors as shown in Figure 2. In both methods, capacitor Cn voltage represents the inductor total currents. A droop amplifier converts Cn voltage into an internal current source with the gain set by resistor Ri.
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The current source is used for load line implementation, current monitor and overcurrent protection. Figure 12 shows the load line implementation. The ISL62881 drives a current source Idroop out of the FB pin, described by Equation 1.
2xV Cn I droop = ----------------Ri (EQ. 1)
When using inductor DCR current sensing, a single NTC element is used to compensate the positive temperature coefficient of the copper winding thus sustaining the load line accuracy with reduced cost. Idroop flows through resistor Rdroop and creates a voltage drop as shown in Equation 2.
V droop = R droop x I droop (EQ. 2)
load release to achieve fast response. On the other hand, the switching frequency is relatively constant at steady state. Variation is expected when the power stage condition, such as input voltage, output voltage, load, etc. changes. The variation is usually less than 15% and doesn't have any significant effect on output voltage ripple magnitude. Equation 5 gives an estimate of the frequency-setting resistor Rfset value. 8k RFSET gives approximately 300kHz switching frequency. Lower resistance gives higher switching frequency.
R FSET ( k ) = ( Period ( s ) - 0.29 ) x 2.65 (EQ. 5)
Modes of Operation
TABLE 2. ISL62881 MODES OF OPERATION CONFIGURATION DPRSLPVR CPU VR Application GPU VR Application 0 1 0 1 OPERATIONAL VOLTAGE MODE SLEW RATE 1-phase CCM 1-phase DE 1-phase CCM 1-phase DE 5mV/s 10mV/s 5mV/s
Vdroop is the droop voltage required to implement load line. Changing Rdroop or scaling Idroop can both change the load line slope. Since Idroop also sets the overcurrent protection level, it is recommended to first scale Idroop based on OCP requirement, then select an appropriate Rdroop value to obtain the desired load line slope.
Differential Sensing
Figure 12 also shows the differential voltage sensing scheme. VCCSENSE and VSSSENSE are the remote voltage sensing signals from the processor die. A unity gain differential amplifier senses the VSSSENSE voltage and adds it to the DAC output. The error amplifier regulates the inverting and the non-inverting input voltages to be equal, therefore:
VCC SENSE + V
droop
Table 2 shows the ISL62881 operational modes, programmed by the logic status of the DPRSLPVR pin. The ISL62881 enters 1-phase DE mode when there is DPRSLPVR = 1. When the ISL62881 is configured for GPU VR application, DPRSLPVR logic status also controls the output voltage slew rate. The slew rate is 5mV/s for DPRSLPVR = 0 and is 10mV/s for DPRSLPVR = 1.
= V DAC + VSS SENSE
Dynamic Operation
When the ISL62881 is configured for CPU VR application, it responds to VID changes by slewing to the new voltage at 5mV/s slew rate. As the output approaches the VID command voltage, the dv/dt moderates to prevent overshoot. Geyserville-III transitions commands one LSB VID step (12.5mV) every 2.5s, controlling the effective dv/dt at 5mv/s. The ISL62881 is capable of 5mV/s slew rate. When the ISL62881 is configured for GPU VR application, it responds to VID changes by slewing to the new voltage at a slew rate set by the logic status on the DPRSLPVR pin. The slew rate is 5mV/s when DPRSLPVR = 0 and is 10mV/s when DPRSLPVR = 1. When the ISL62881 is in DE mode, it will actively drive the output voltage up when the VID changes to a higher value. It'll resume DE mode operation after reaching the new voltage level. If the load is light enough to warrant DCM, it will enter DCM after the inductor current has crossed zero for four consecutive cycles. The ISL62881 will remain in DE mode when the VID changes to a lower value. The output voltage will decay to the new value and the load will determine the slew rate. The R3TM modulator intrinsically has voltage feed forward. The output voltage is insensitive to a fast slew rate input voltage change.
(EQ. 3)
Rewriting Equation 3 and substituting Equation 2 gives:
VCC SENSE - VSS SENSE = V DAC - R droop x I droop (EQ. 4)
Equation 4 is the exact equation required for load line implementation. The VCCSENSE and VSSSENSE signals come from the processor die. The feedback will be open circuit in the absence of the processor. As shown in Figure 12, it is recommended to add a "catch" resistor to feed the VR local output voltage back to the compensator, and add another "catch" resistor to connect the VR local output ground to the RTN pin. These resistors, typically 10~100, will provide voltage feedback if the system is powered up without a processor installed.
CCM Switching Frequency
The RFSET resistor between the COMP and the VW pins sets the VW windows size, which therefore sets the switching frequency. When the ISL62881 is in continuous conduction mode (CCM), the switching frequency is not absolutely constant due to the nature of the R3TM modulator. As explained in "Multiphase R3TM Modulator" on page 11, the effective switching frequency will increase during load insertion and will decrease during 15
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Protections
The ISL62881 provides overcurrent, undervoltage, and overvoltage protections. The ISL62881 determines overcurrent protection (OCP) by comparing the average value of the droop current Idroop with an internal current source threshold. It declares OCP when Idroop is above the threshold for 120s. A resistor Rcomp from the COMP pin to GND programs the OCP current source threshold, as well as the overshoot reduction function (to be discussed in later sections), as Table 3 shows. It is recommended to use the nominal Rcomp value. The ISL62881 detects the Rcomp value at the beginning of start-up, and sets the internal OCP threshold accordingly. It remembers the Rcomp value until the VR_ON signal drops below the POR threshold.
TABLE 3. ISL62881 OCP THRESHOLD AND OVERSHOOT REDUCTION FUNCTION Rcomp MIN (k) 305 205 155 104 78 62 45 NOMINAL (k) none 400 235 165 120 85 66 50 MAX (k) none 410 240 170 130 90 68 55 OCP THRESHOLD (A) 20 22.67 20.67 18 20 22.67 20.67 18 Enabled FAULT TYPE Overcurrent Way-Overcurrent (2.5xOC) Overvoltage +200mV Undervoltage -300mV Overvoltage 1.55V Immediately Low-side VDD MOSFET on toggle until Vcore <0.85V, then PWM tri-state, PGOOD latched low. OVERSHOOT REDUCTION FUNCTION Disabled
VR_ON low or by bringing VDD below the POR threshold. When VR_ON and VDD return to their high operating levels, a soft-start will occur. The second level of overvoltage protection is different. If the output voltage exceeds 1.55V, the ISL62881 will immediately declare an OV fault, de-assert PGOOD, and turn on the low-side power MOSFETs. The low-side power MOSFETs remain on until the output voltage is pulled down below 0.85V when all power MOSFETs are turned off. If the output voltage rises above 1.55V again, the protection process is repeated. This behavior provides the maximum amount of protection against shorted high-side power MOSFETs while preventing output ringing below ground. Resetting VR_ON cannot clear the 1.55V OVP. Only resetting VDD will clear it. The 1.55V OVP is active all the time when the controller is enabled, even if one of the other faults have been declared. This ensures that the processor is protected against high-side power MOSFET leakage while the MOSFETs are commanded off. Table 4 summarizes the fault protections.
TABLE 4. FAULT PROTECTION SUMMARY FAULT PROTECTI DURATION ON BEFORE ACTION PROTECTION 120s <2s 1ms PWM tristate, PGOOD latched low
FAULT RESET VR_ON toggle or VDD toggle
The default OCP threshold is the value when Rcomp is not populated. It is recommended to scale the droop current Idroop such that the default OCP threshold gives approximately the desired OCP level, then use Rcomp to fine tune the OCP level if necessary. For overcurrent condition above 2.5x the OCP level, the PWM output will immediately shut off and PGOOD will go low to maximize protection. This protection is also referred to as way-overcurrent protection or fastovercurrent protection, for short-circuit protections. The ISL62881 will declare undervoltage (UV) fault and latch off if the output voltage is less than the VID set value by 300mV or more for 1ms. It'll turn off the PWM output and de-assert PGOOD. The ISL62881 has two levels of overvoltage protections. The first level of overvoltage protection is referred to as PGOOD overvoltage protection. If the output voltage exceeds the VID set value by +200mV for 1ms, the ISL62881 will declare a fault and de-assert PGOOD. The ISL62881 takes the same actions for all of the above fault protections: deassertion of PGOOD and turn-off of the high-side and low-side power MOSFETs. Any residual inductor current will decay through the MOSFET body diodes. These fault conditions can be reset by bringing
Current Monitor
The ISL62881 provides the current monitor function. The IMON pin outputs a high-speed analog current source that is 3 times of the droop current flowing out of the FB pin. Thus as shown by Equation 6.
I IMON = 3 x I droop (EQ. 6)
As Figures 1 and 2 show, a resistor Rimon is connected to the IMON pin to convert the IMON pin current to voltage. A capacitor can be paralleled with Rimon to filter the voltage information. The IMVP-6.5TM specification requires that the IMON voltage information be referenced to VSSSENSE. The IMON pin voltage range is 0V to 1.1V. A clamp circuit prevents the IMON pin voltage from going above 1.1V.
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Adaptive Body Diode Conduction Time Reduction
In DCM, the controller turns off the low-side MOSFET when the inductor current approaches zero. During on-time of the low-side MOSFET, phase voltage is negative and the amount is the MOSFET RDS(ON) voltage drop, which is proportional to the inductor current. A phase comparator inside the controller monitors the phase voltage during on-time of the low-side MOSFET and compares it with a threshold to determine the zero-crossing point of the inductor current. If the inductor current has not reached zero when the low-side MOSFET turns off, it'll flow through the low-side MOSFET body diode, causing the phase node to have a larger voltage drop until it decays to zero. If the inductor current has crossed zero and reversed the direction when the low-side MOSFET turns off, it'll flow through the high-side MOSFET body diode, causing the phase node to have a spike until it decays to zero. The controller continues monitoring the phase voltage after turning off the low-side MOSFET and adjusts the phase comparator threshold voltage accordingly in iterative steps such that the low-side MOSFET body diode conducts for approximately 40ns to minimize the body diode-related loss. at a high repetitive rate. User discretion is advised when this function is enabled.
Key Component Selection
RBIAS
The ISL62881 uses a resistor (1% or better tolerance is recommended) from the RBIAS pin to GND to establish highly accurate reference current sources inside the IC. Using RBIAS = 147k sets the controller for CPU core application and using Rbias = 47k sets the controller for GPU core application. Do not connect any other components to this pin. Do not connect any capacitor to the RBIAS pin as it will create instability. Care should be taken in layout that the resistor is placed very close to the RBIAS pin and that a good quality signal ground is connected to the opposite side of the RBIAS resistor.
Ris and Cis
As Figures 1 and 2 show, the ISL62881 needs the Ris - Cis network across the ISUM+ and the ISUM- pins to stabilize the droop amplifier. The preferred values are Ris = 82.5 and Cis = 0.01F. Slight deviations from the recommended values are acceptable. Large deviations may result in instability.
Overshoot Reduction Function
The ISL62881 has an optional overshoot reduction function, enabled or disabled by the resistor from the COMP pin to GND, as shown in Table 3. When a load release occurs, the energy stored in the inductors will dump to the output capacitor, causing output voltage overshoot. The inductor current freewheels through the low-side MOSFET during this period of time. The overshoot reduction function turns off the low-side MOSFET during the output voltage overshoot, forcing the inductor current to freewheel through the low-side MOSFET body diode. Since the body diode voltage drop is much higher than MOSFET RDS(ON) voltage drop, more energy is dissipated on the low-side MOSFET therefore the output voltage overshoot is lower. If the overshoot reduction function is enabled, the ISL62881 monitors the COMP pin voltage to determine the output voltage overshoot condition. The COMP voltage will fall and hit the clamp voltage when the output voltage overshoots. The ISL62881 will turn off LGATE when COMP is being clamped. The low-side MOSFET in the power stage will be turned off. When the output voltage has reached its peak and starts to come down, the COMP voltage starts to rise and is no longer clamped. The ISL62881 will resume normal PWM operation. While the overshoot reduction function reduces the output voltage overshoot, energy is dissipated on the low-side MOSFET, causing additional power loss. The more frequent the transient event, the more power loss is dissipated on the low-side MOSFET. The MOSFET may face severe thermal stress when transient events happen
Inductor DCR Current-Sensing Network
PHASE
RSUM
ISUM+
L
RNTCS RP + CN VCN -
DCR
RNTC RI ISUM-
IO
FIGURE 13. DCR CURRENT-SENSING NETWORK
Figure 13 shows the inductor DCR current-sensing network for a 2-phase solution. An inductor current flows through the DCR and creates a voltage drop. The inductor has a resistors in Rsum connected to the phasenode-side pad and a PCB trace connected to the outputside pad to accurately sense the inductor current by sensing the DCR voltage drop. The sensed current information is fed to the NTC network (consisting of Rntcs, Rntc and Rp) and capacitor Cn. Rntc is a negative temperature coefficient (NTC) thermistor, used to temperature-compensate the inductor DCR change. The inductor current information is presented to the capacitor Cn. Equations 7 through 11 describe the frequency-
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domain relationship between inductor total current Io(s) and Cn voltage VCn(s):
R ntcnet V Cn ( s ) = ----------------------------------------- x DCR x I o ( s ) x A cs ( s ) R ntcnet + R sum ( R ntcs + R ntc ) x R p R ntcnet = ---------------------------------------------------R ntcs + R ntc + R p s 1 + -----L A cs ( s ) = ---------------------s 1 + ----------- sns (EQ. 7) L C n = -------------------------------------------------------------R ntcnet x R sum ----------------------------------------- x DCR R ntcnet + R sum (EQ. 12)
(EQ. 8)
io
(EQ. 9)
Vo
FIGURE 14. DESIRED LOAD TRANSIENT RESPONSE WAVEFORMS
DCR L = ------------L 1 sns = ------------------------------------------------------R ntcnet x R sum ----------------------------------------- x C n R ntcnet + R sum
(EQ. 10)
io
(EQ. 11)
Transfer function Acs(s) always has unity gain at DC. The inductor DCR value increases as the winding temperature increases, giving higher reading of the inductor DC current. The NTC Rntc values decreases as its temperature decreases. Proper selections of Rsum, Rntcs, Rp and Rntc parameters ensure that VCn represents the inductor total DC current over the temperature range of interest. There are many sets of parameters that can properly temperature-compensate the DCR change. Since the NTC network and the Rsum resistors form a voltage divider, Vcn is always a fraction of the inductor DCR voltage. It is recommended to have a higher ratio of Vcn to the inductor DCR voltage, so the droop circuit has higher signal level to work with. A typical set of parameters that provide good temperature compensation are: Rsum = 3.65k, Rp = 11k, Rntcs = 2.61k and Rntc = 10k (ERT-J1VR103J). The NTC network parameters may need to be fine tuned on actual boards. One can apply full load DC current and record the output voltage reading immediately; then record the output voltage reading again when the board has reached the thermal steady state. A good NTC network can limit the output voltage drift to within 2mV. It is recommended to follow the Intersil evaluation board layout and current-sensing network parameters to minimize engineering time. VCn(s) also needs to represent real-time Io(s) for the controller to achieve good transient response. Transfer function Acs(s) has a pole sns and a zero L. One needs to match L and sns so Acs(s) is unity gain at all frequencies. By forcing L equal to sns and solving for the solution, Equation 12 gives Cn value.
Vo
FIGURE 15. LOAD TRANSIENT RESPONSE WHEN Cn IS TOO SMALL
io
Vo
FIGURE 16. LOAD TRANSIENT RESPONSE WHEN Cn IS TOO LARGE
For example, given Rsum = 3.65k, Rp = 11k, Rntcs = 2.61k, Rntc = 10k, DCR = 1.1m and L = 0.45H, Equation 12 gives Cn = 0.18F. Assuming the compensator design is correct, Figure 14 shows the expected load transient response waveforms if Cn is correctly selected. When the load current Icore has a square change, the output voltage Vcore also has a square response. If Cn value is too large or too small, VCn(s) will not accurately represent real-time Io(s) and will worsen the transient response. Figure 15 shows the load transient response when Cn is too small. Vcore will sag excessively upon load insertion and may create a system failure. Figure 16 shows the transient response when Cn is too large. Vcore is sluggish in drooping to its final value. There will be excessive overshoot if load insertion occurs during this time, which may potentially hurt the CPU reliability.
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that two capacitors Cn.1 and Cn.2 are in parallel. Resistor Rn is an optional component to reduce the Vo ring back. At steady state, Cn.1 + Cn.2 provides the desired Cn capacitance. At the beginning of io change, the effective capacitance is less because Rn increases the impedance of the Cn.1 branch. As Figure 15 explains, Vo tends to dip when Cn is too small, and this effect will reduce the Vo ring back. This effect is more pronounced when Cn.1 is much larger than Cn.2. It is also more pronounced when Rn is bigger. However, the presence of Rn increases the ripple of the Vn signal if Cn.2 is too small. It is recommended to keep Cn.2 greater than 2200pF. Rn value usually is a few ohms. Cn.1, Cn.2 and Rn values should be determined through tuning the load transient response waveforms on an actual board. Rip and Cip form an R-C branch in parallel with Ri, providing a lower impedance path than Ri at the beginning of io change. Rip and Cip do not have any effect at steady state. Through proper selection of Rip and Cip values, idroop can resemble io rather than iL, and Vo will not ring back. The recommended value for Rip is 100. Cip should be determined through tuning the load transient response waveforms on an actual board. The recommended range for Cip is 100pF~2000pF. However, it should be noted that the Rip -Cip branch may distort the idroop waveform. Instead of being triangular as the real inductor current, idroop may have sharp spikes, which may adversely affect idroop average value detection and therefore may affect OCP accuracy. User discretion is advised.
iO
iL
VO
RING BACK
FIGURE 17. OUTPUT VOLTAGE RING BACK PROBLEM
ISUM+
Rntcs Rp Rntc
Cn.1 Rn OPTIONAL
+ Cn.2 Vcn ISUM-
Ri
Rip Cip
OPTIONAL
FIGURE 18. OPTIONAL CIRCUITS FOR RING BACK REDUCTION
Figure 17 shows the output voltage ring back problem during load transient response. The load current io has a fast step change, but the inductor current iL cannot accurately follow. Instead, iL responds in first order system fashion due to the nature of current loop. The ESR and ESL effect of the output capacitors makes the output voltage Vo dip quickly upon load current change. However, the controller regulates Vo according to the droop current idroop, which is a real-time representation of iL; therefore it pulls Vo back to the level dictated by iL, causing the ring back problem. This phenomenon is not observed when the output capacitors have very low ESR and ESL, such as all ceramic capacitors. Figure 18 shows two optional circuits for reduction of the ring back. Rip and Cip form an R-C branch in parallel with Ri, providing a lower impedance path than Ri at the beginning of io change. Rip and Cip do not have any effect at steady state. Through proper selection of Rip and Cip values, idroop can resemble io rather than iL, and Vo will not ring back. The recommended value for Rip is 100W. Cip should be determined through tuning the load transient response waveforms on an actual board. The recommended range for Cip is 100pF~2000pF. Cn is the capacitor used to match the inductor time constant. It usually takes the parallel of two (or more) capacitors to get the desired value. Figure 18 shows
Resistor Current-Sensing Network
PHASE
L
DCR RSUM RSEN ISUM+
Vcn
Cn Ri
ISUM-
Io
FIGURE 19. RESISTOR CURRENT-SENSING NETWORK
Figure 19 shows the resistor current-sensing network. The inductor has a series current-sensing resistor Rsen. Rsum and is connected to the Rsen pad to accurately capture the inductor current information. The Rsum feeds the sensed information to capacitor Cn. Rsum and Cn
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form a a filter for noise attenuation. Equations 13 through 15 gives VCn(s) expressions:
V Cn ( s ) = R sen x I o ( s ) x A Rsen ( s ) (EQ. 13)
Substitution of Equation 20 into Equation 1 gives Equation 21:
2 I droop = ---- x R sen x I o Ri (EQ. 21)
Therefore:
1 A Rsen ( s ) = ---------------------s -----------1+ sns 1 Rsen = ---------------------------R sum x C n (EQ. 14) 2R sen x I o R i = --------------------------I droop (EQ. 22)
(EQ. 15)
Substitution of Equation 22 and application of the OCP condition in Equation 18 gives:
2R sen x I omax R i = --------------------------------------I droopmax (EQ. 23)
Transfer function ARsen(s) always has unity gain at DC. Current-sensing resistor Rsen value will not have significant variation over-temperature, so there is no need for the NTC network. The recommended values are Rsum = 1k and Cn = 5600pF.
where Iomax is the full load current, Idroopmax is the corresponding droop current. For example, given Rsen = 1m, Iomax = 14A and Idroopmax = 14A, Equation 23 gives Ri = 2k. A resistor from COMP to GND can adjust the internal OCP threshold, providing another dimension of fine-tune flexibility. Table 3 shows the detail. It is recommended to scale Idroop such that the default OCP threshold gives approximately the desired OCP level, then use Rcomp to fine tune the OCP level if necessary.
Overcurrent Protection
Referring to Equation 1 and Figures 12, 13 and 19, resistor Ri sets the droop current Idroop. Table 3 shows the internal OCP threshold. It is recommended to design Idroop without using the Rcomp resistor. For example, the OCP threshold is 20A. We will design Idroop to be 14A at full load, so the OCP trip level is 1.43x of the full load current. For inductor DCR sensing, Equation 16 gives the DC relationship of Vcn(s) and Io(s).
R ntcnet V Cn = ----------------------------------------- x DCR x I o R ntcnet + R sum (EQ. 16)
Load Line Slope
Refer to Figure 12. For inductor DCR sensing, substitution of Equation 17 into Equation 2 gives the load line slope expression in Equation 24.
2R droop R ntcnet V droop LL = ------------------ = ---------------------- x ----------------------------------------- x DCR Io Ri R ntcnet + R sum (EQ. 24)
Substitution of Equation 16 into Equation 1 gives:
R ntcnet 2 I droop = ---- x ----------------------------------------- x DCR x I o R i R ntcnet + R sum (EQ. 17)
For resistor sensing, substitution of Equation 21 into Equation 2 gives the load line slope expression in Equation 25:
2R sen x R droop V droop LL = ------------------ = -----------------------------------------Io Ri (EQ. 25)
Therefore:
2R ntcnet x DCR x I o R i = --------------------------------------------------------------------( R ntcnet + R sum ) x I droop (EQ. 18)
Substitution of Equation 8 and application of the OCP condition in Equation 18 gives:
( R ntcs + R ntc ) x R p 2 x ---------------------------------------------------- x DCR x I omax R ntcs + R ntc + R p R i = ----------------------------------------------------------------------------------------------------------------( R ntcs + R ntc ) x R p ---------------------------------------------------- + R sum x I droopmax R ntcs + R ntc + R p (EQ. 19)
Substitution of Equation 18 and rewriting Equation 24, or substitution of Equation 22 and rewriting Equation 25 gives the same result in Equation 26:
Io R droop = ---------------- x LL I droop (EQ. 26)
One can use the full load condition to calculate Rdroop. For example, given Iomax = 14A, Idroopmax = 14A and LL = 7m, Equation 26 gives Rdroop = 7k. It is recommended to start with the Rdroop value calculated by Equation 26, and fine tune it on the actual board to get accurate load line slope. One should record the output voltage readings at no load and at full load for load line slope calculation. Reading the output voltage at lighter load instead of full load will increase the measurement error.
where Iomax is the full load current, Idroopmax is the corresponding droop current. For example, given Rsum = 3.65k, Rp = 11k, Rntcs = 2.61k, Rntc = 10k, DCR = 1.1m, Iomax = 14A and Idroopmax = 14A, Equation 19 gives Ri = 1.36k. For resistor sensing, Equation 20 gives the DC relationship of Vcn(s) and Io(s).
V Cn = R sen x I o (EQ. 20)
20
FN6924.1 February 25, 2010
ISL62881, ISL62881B
Current Monitor
Referring to Equation 6 for the IMON pin current expression. Refer to Figures 1 and 2, the IMON pin current flows through Rimon. The voltage across Rimon is shown in Equation 27:
V Rimon = 3 x I droop x R imon (EQ. 27)
inductor current, multiplies it by a gain of the load line slope, then adds it on top of the sensed output voltage and feeds it to the compensator. T(1) is measured after the summing node, and T2(s) is measured in the voltage loop before the summing node. The spreadsheet gives both T1(s) and T2(s) plots. However, only T2(s) can be actually measured on an ISL62881 regulator. T1(s) is the total loop gain of the voltage loop and the droop loop. It always has a higher crossover frequency than T2(s) and has more meaning of system stability. T2(s) is the voltage loop gain with closed droop loop. It has more meaning of output voltage response. Design the compensator to get stable T1(s) and T2(s) with sufficient phase margin, and output impedance equal or smaller than the load line slope.
L Q1 VIN GATE Q2 DRIVER COUT IO VO
Rewriting Equation 26 gives Equation 28:
Io I droop = ------------------ x LL R droop (EQ. 28)
Substitution of Equation 28 into Equation 27 gives Equation 29:
3I o x LL V Rimon = --------------------- x R imon R droop (EQ. 29)
Rewriting Equation 29 and application of full load condition gives Equation 30:
V Rimon x R droop R imon = ---------------------------------------------3I o x LL (EQ. 30)
LOAD LINE SLOPE
For example, given LL = 7m, Rdroop = 7k, VRimon = 963mV at Iomax = 14A, Equation 30 gives Rimon = 22.9k. A capacitor Cimon can be paralleled with Rimon to filter the IMON pin voltage. The RimonCimon time constant is the user's choice. It is recommended to have a time constant long enough such that switching frequency ripples are removed.
MOD EA + COMP CHANNEL B CHANNEL A CHANNEL A NETWORK ANALYZER
20
+
+
VID
ISOLATION TRANSFORMER
LOOP GAIN =
CHANNEL B EXCITATION OUTPUT
Compensator
Figure 14 shows the desired load transient response waveforms. Figure 20 shows the equivalent circuit of a voltage regulator (VR) with the droop function. A VR is equivalent to a voltage source (=VID) and output impedance Zout(s). If Zout(s) is equal to the load line slope LL, i.e. constant output impedance, in the entire frequency range, Vo will have square response when Io has a square change.
Zout(s) = LL iO + VO -
FIGURE 21. LOOP GAIN T1(s) MEASUREMENT SET-UP
L Q1 VIN GATE Q2 DRIVER COUT
VO
IO
LOAD LINE SLOPE + MOD COMP EA + + 20
VID
VR
LOAD
VID
FIGURE 20. VOLTAGE REGULATOR EQUIVALENT
LOOP GAIN =
CHANNEL B CHANNEL A CHANNEL A NETWORK ANALYZER
ISOLATION TRANSFORMER
A VR with active droop function is a dual-loop system consisting of a voltage loop and a droop loop which is a current loop. However, neither loop alone is sufficient to describe the entire system. The spreadsheet shows two loop gain transfer functions, T1(s) and T2(s), that describe the entire system. Figure 21 conceptually shows T1(s) measurement set-up and Figure 22 conceptually shows T2(s) measurement set-up. The VR senses the 21
CHANNEL B EXCITATION OUTPUT
FIGURE 22. LOOP GAIN T2(s) MEASUREMENT SET-UP
FN6924.1 February 25, 2010
ISL62881, ISL62881B
Optional Slew Rate Compensation Circuit For 1-Tick VID Transition
When Vcore increases, the time domain expression of the induced Idroop change is as shown in Equation 31:
-------------------------- C out x LL dV core C x LL I droop ( t ) = ------------------------- x ------------------ x 1 - e out R droop dt
Vcore OPTIONAL FB Ivid Idroop_vid E/A
-t
(EQ. 31)
Rdroop Rvid Cvid
where Cout is the total output capacitance. In the meantime, the Rvid-Cvid branch current Ivid time domain expression is as shown in Equation 32:
------------------------------- dV fb R x C vid I vid ( t ) = C vid x ------------ x 1 - e vid dt -t
(EQ. 32)
COMP
VDACDAC
X1
VIDs
VID<0:6> VSSSENSE
RTN INTERNAL TO IC VSS
It is desired to let Ivid(t) cancel Idroop_vid(t). So there are:
dV fb C out x LL dV core C vid x ------------ = ------------------------- x -----------------dt dt R droop (EQ. 33)
and:
VID<0:6>
R vid x C vid = C out x LL
(EQ. 34)
Vfb
The result is:
R vid = R droop (EQ. 35)
Ivid
and:
dV core C out x LL -----------------dt C vid = ------------------------- x -----------------R droop dV fb -----------dt (EQ. 36)
Vcore
Idroop_vid
FIGURE 23. OPTIONAL SLEW RATE COMPENSATION CIRCUIT FOR1-TICK VID TRANSITION
For example: given LL = 3m, Rdroop = 4.22k, Cout = 1320F, dVcore/dt = 5mV/s and dVfb/dt = 15mV/s, Equation 35 gives Rvid = 4.22k and Equation 36 gives Cvid = 227pF. It's recommended to select the calculated Rvid value and start with the calculated Cvid value and tweak it on the actual board to get the best performance. During normal transient response, the FB pin voltage is held constant, therefore is virtual ground in small signal sense. The Rvid-Cvid network is between the virtual ground and the real ground, and hence has no effect on transient response.
During a large VID transition, the DAC steps through the VIDs at a controlled slew rate of 2.5s or 1.25s per tick (12.5mV), controlling output voltage Vcore slew rate at 5mV/s or 10mV/s. Figure 23 shows the waveforms of 1-tick VID transition. During 1-tick VID transition, the DAC output changes at approximately 15mV/s slew rate, but the DAC cannot step through multiple VIDs to control the slew rate. Instead, the control loop response speed determines Vcore slew rate. Ideally, Vcore will follow the FB pin voltage slew rate. However, the controller senses the inductor current increase during the up transition, as the Idroop_vid waveform shows, and will droop the output voltage Vcore accordingly, making Vcore slew rate slow. Similar behavior occurs during the down transition. To control Vcore slew rate during 1-tick VID transition, one can add the Rvid-Cvid branch, whose current Ivid cancels Idroop_vid.
Voltage Regulator Thermal Throttling
Figure 24 shows the thermal throttling feature with hysteresis. An NTC network is connected between the NTC pin and GND. At low temperature, SW1 is on and SW2 connects to the 1.20V side. The total current flowing out of the NTC pin is 60A. The voltage on NTC pin is higher than the threshold voltage of 1.20V and the comparator output is low. VR_TT# is pulled up by the external resistor.
22
FN6924.1 February 25, 2010
ISL62881, ISL62881B
For example, given Panasonic NTC thermistor with B = 4700, the resistance will drop to 0.03322 of its nominal at +105C, and drop to 0.03956 of its nominal at +100C. If the required temperature hysteresis is +105C to +100C, the required resistance of NTC will be as shown in Equation 38:
2.96k ----------------------------------------------------- = 467k ( 0.03956 - 0.03322 ) (EQ. 38)
54
64
SW1 NTC VNTC + RNTC Rs 1.24V SW2 1.20V INTERNAL TO ISL62881 +
VR_TT#
Therefore, a larger value thermistor such as 470k NTC should be used. At +105C, 470k NTC resistance becomes (0.03322 x 470k) = 15.6k. With 60A on the NTC pin, the voltage is only (15.6k x 60A) = 0.937V. This value is much lower than the threshold voltage of 1.20V. Therefore, a regular resistor needs to be in series with the NTC. The required resistance can be calculated by Equation 39:
1.20V --------------- - 15.6k = 4.4k 60A (EQ. 39)
FIGURE 24. CIRCUITRY ASSOCIATED WITH THE THERMAL THROTTLING FEATURE OF THE ISL62881
When temperature increases, the NTC thermistor resistance decreases so the NTC pin voltage drops. When the NTC pin voltage drops below 1.20V, the comparator changes polarity and turns SW1 off and throws SW2 to 1.24V. This pulls VR_TT# low and sends the signal to start thermal throttle. There is a 6A current reduction on NTC pin and 40mV voltage increase on threshold voltage of the comparator in this state. The VR_TT# signal will be used to change the CPU operation and decrease the power consumption. When the temperature drops down, the NTC thermistor voltage will go up. If NTC voltage increases to above 1.24V, the comparator will flip back. The external resistance difference in these two conditions is shown in Equation 37:
1.24V 1.20V --------------- - --------------- = 2.96k 54A 60A (EQ. 37)
4.42k is a standard resistor value. Therefore, the NTC branch should have a 470k NTC and 4.42k resistor in series. The part number for the NTC thermistor is ERTJ0EV474J. It is a 0402 package. NTC thermistor will be placed in the hot spot of the board.
Layout Guidelines
Table 5 shows the layout considerations. The designators refer to the reference designs shown in Figures 25 and 26.
One needs to properly select the NTC thermistor value such that the required temperature hysteresis correlates to 2.96k resistance change. A regular resistor may need to be in series with the NTC thermistor to meet the threshold voltage values.
TABLE 5. LAYOUT CONSIDERATIONS NAME GND LAYOUT CONSIDERATION Create analog ground plane underneath the controller and the analog signal processing components. Don't let the power ground plane overlap with the analog ground plane. Avoid noisy planes/traces (e.g.: phase node) from crossing over/overlapping with the analog plane. No special consideration. No special consideration Place the RBIAS resistor (R16) in general proximity of the controller. Low impedance connection to the analog ground plane. No special consideration. The NTC thermistor (R9) needs to be placed close to the thermal source that is monitor to determine thermal throttling. Usually it's placed close to phase-1 high-side MOSFET. Place capacitor (C4) across VW and COMP in close proximity of the controller. Place compensator components (C3, C5, C6 R7, R11, R10 and C11) in general proximity of the controller.
CLK_EN# PGOOD RBIAS VR_TT# NTC VW COMP FB
23
FN6924.1 February 25, 2010
ISL62881, ISL62881B
TABLE 5. LAYOUT CONSIDERATIONS (Continued) NAME VSEN RTN VDD IMON ISUMISUM+ A capacitor (C16) decouples it to GND. Place it in close proximity of the controller. Place the filter capacitor (C21) close to the CPU. Place the current sensing circuit in general proximity of the controller. Place C82 very close to the controller. Place NTC thermistors R42 next to inductor (L1) so it senses the inductor temperature correctly. The power stage sends a pair of VSUM+ and VSUM- signals to the controller. Run these two signal traces in parallel fashion with decent width (>20mil). IMPORTANT: Sense the inductor current by routing the sensing circuit to the inductor pads. Route R63 to the phase-node side pad of inductor L1. Route the other current sensing trace to the output side pad of inductor L1. If possible, route the traces on a different layer from the inductor pad layer and use vias to connect the traces to the center of the pads. If no via is allowed on the pad, consider routing the traces into the pads from the inside of the inductor. The following drawings show the two preferred ways of routing current sensing traces.
INDUCTOR INDUCTOR
LAYOUT CONSIDERATION Place the VSEN/RTN filter (C12, C13) in close proximity of the controller for good decoupling.
VIAS CURRENTSENSING TRACES CURRENTSENSING TRACES
VIN BOOT UGATE PHASE
A capacitor (C17) decouples it to GND. Place it in close proximity of the controller. Use decent wide trace (>30mil). Avoid any sensitive analog signal trace from crossing over or getting close. Run these two traces in parallel fashion with decent width (>30mil). Avoid any sensitive analog signal trace from crossing over or getting close. Recommend routing PHASE trace to the high-side MOSFET (Q2 and Q8) source pins instead of general phase node copper.
VSSP Run these two traces in parallel fashion with decent width (>30mil). Avoid any sensitive analog signal trace from crossing over or getting close. Recommend routing VSSP to the low-side MOSFET (Q3 and Q9) source pins instead LGATE of general power ground plane for better performance. or LGATEa and LGATEb VCCP VID0~6 VR_ON A capacitor (C22) decouples it to GND. Place it in close proximity of the controller. No special consideration. No special consideration.
DPRSLPVR No special consideration. Phase Node Minimize phase node copper area. Don't let the phase node copper overlap with/getting close to other sensitive traces. Cut the power ground plane to avoid overlapping with phase node copper. Minimize the loop consisting of input capacitor, high-side MOSFETs and low-side MOSFETs (e.g.: C27, C33, Q2, Q8, Q3 and Q9).
24
FN6924.1 February 25, 2010
VID0 VID1 VID2 VID3 VID4 VID5 VID6 VR_ON DPRSLPVR +3.3V
IN IN IN IN IN IN IN IN IN
VIN
IN
IN
10UF C33
10UF
56UF
C27
C24
1.91K R23
IRF7821
R19
TBD
Q2 L1
DPRSLPVR
10UF
10UF
10UF
10UF
10UF
10UF
10UF
------R4
DNP ------R6
C60
C59
C40
C56
C55
1000PF
R16
10K
47K
3 4 5 6 7 29
PGOOD RBIAS VW COMP FB VSEN EP R20 0 R37 1 ISL62881HRZ U6
VID0 VCCP LGATE VSSP PHASE UGATE
19 18 17 16 15
----
--------
DNP DNP --------
C83 R110
OPTIONAL ----
RTN ISUMISUM+ VDD VIN IMON BOOT
C6 C3
C4
IN
+5V
0
0.22UF
Q3
R10 R7 R17 10
IN IN
C11
15PF
2.37K 270PF
R11
----C12
1000PF 330PF -----
---- 100PF VCORE IN
422K
6.98K OPTIONAL -------
8 9 10 11 12 13 14
C22
1UF
C54
C61
C41
C52
2
20
10UF
CLK_EN#
R56
C30
IRF7832
470UF
PGOOD OPTIONAL ----
OUT
VR_ON VID6 VID5 VID4 VID3 VID2
28 27 26 25 24 23 22
1
VID1
21
0.88UH
OUT
VCORE
R50
R18 10
1UF C17
C13
C16
VSSSENSE
0.22UF
0
C21
IN
3900PF
22.6K
0.01UF 82.5
10K 2.61K NTC
0.056UF
R26
0.15UF
R41
R38
R30
0.1UF
----
----
C20
3.01K -----------C81 R109
-----> R42
C15
11K
C82
C18
25
FN6924.1 February 25, 2010
ISL62881, ISL62881B
OUT
VCCSENSE
R40
IN
+5V VIN
IMON
IN
R63
VSSSENSE LAYOUT NOTE:
3.65K
ROUTE UGATE TRACE IN PARALLEL WITH THE PHASE TRACE GOING TO THE SOURCE OF Q2 ROUTE LGATE TRACE IN PARALLEL WITH THE VSSP TRACE GOING TO THE SOURCE OF Q3
DNP DNP -----------OPTIONAL
PLACE NEAR L1
FIGURE 25. GPU APPLICATION REFERENCE DESIGN
VID0 VID1 VID2 VID3 VID4 VID5 VID6 VR_ON DPRSLPVR +3.3V
IN IN IN IN IN IN IN IN IN
VIN
IN
IN
10UF C33
10UF
56UF
C27
C24
1.91K
10K R23
IRF7821
R19
Q2 L1
330UF
10UF
10UF
10UF
10UF
10UF
-------
DNP ------R6
C60
C59
C40
7.32K
1000PF
R16 147K
R4
3 4 5 6 7 29
PGOOD RBIAS VW COMP FB VSEN EP R20 ISL62881HRZ U6
VID0 VCCP LGATE VSSP PHASE UGATE
19 18 17 16 15
10UF
10UF
10UF
10UF
10UF
--------
C83 R110
DNP DNP --------
OPTIONAL ----
RTN ISUMISUM+ VDD VIN IMON BOOT
C6 C3
R10 R7 R11
C11
27PF
4.87K 470PF 4.22K
C22
1UF
10UF
10UF
10UF
10UF
10UF
1000PF 330PF -----
----C12
100PF 422K ---R17 VCORE IN VCCSENSE VSSSENSE
10
IN IN
10UF
C43
C42
C50
C49
C48
8 9 10 11 12 13 14
C47
10UF
----
C4
IN
+5V
0
0.22UF
Q3
Q9
C55
C54
C75
C74
C70
C71
C56
C61
C41
C39
C52
2
20
10UF
CLK_EN#
R56
C30
IRF7832
IRF7832
330UF
CLK_EN# OUT PGOOD OUT OPTIONAL ----
DPRSLPVR
VR_ON VID6 VID5 VID4 VID3 VID2
28 27 26 25 24 23 22
1
VID1
21
0.45UH
OUT
VCORE
10UF
10UF
10UF
10UF
10UF
R50
R18 10
0.22UF
1UF C17
C13
C16
0
34K
C21
----
1
IN
2700PF
R40
IN
R63
VSSSENSE LAYOUT NOTE:
0.01UF 82.5
10K 2.61K NTC
0.022UF
R26
0.15UF
3.65K
R41
R30
----
----
0.1UF
C20
1.91K ----------C81 R109 DNP DNP ----------OPTIONAL
-----> R42
ROUTE UGATE TRACE IN PARALLEL WITH THE PHASE TRACE GOING TO THE SOURCE OF Q2 AND Q8 ROUTE LGATE TRACE IN PARALLEL WITH THE VSSP TRACE GOING TO THE SOURCE OF Q3 AND Q9
R38
C15
FIGURE 26. CPU APPLICATION REFERENCE DESIGN
11K
C82
C18
PLACE NEAR L1
10UF
C68
C66
C65
C67
C64
C63
26
FN6924.1 February 25, 2010
ISL62881, ISL62881B
----
0 R37
OUT IN
OPTIONAL
+5V VIN
IMON
ISL62881, ISL62881B
CPU Application Reference Design Bill of Materials
QTY REFERENCE 1 1 1 1 2 1 1 1 2 1 2 1 2 C11 C12 C13 C15 C16, C22 C18 C20 C21 C17, C30 C24 C27, C33 C3 C39, C52 VALUE 470pF 330pF DESCRIPTION Multilayer Cap, 16V, 10% Multilayer Cap, 16V, 10% MANUFACTURER GENERIC GENERIC GENERIC GENERIC GENERIC GENERIC GENERIC GENERIC GENERIC SANYO GENERIC GENERIC PANASONIC KEMET GENERIC MURATA TDK PART NUMBER H1045-00471-16V10 H1045-00331-16V10 H1045-00102-16V10 H1045-00103-16V10 H1045-00105-16V20 H1045-00154-16V10 H1045-00104-16V10 H1045-00272-16V10 H1045-00224-25V10 25SP56M H1065-00106-25V20 H1045-00101-16V10 EEXSX0D331E4 T520V337M2R5A(1)E4R5-6666 H1045-00102-16V10 GRM21BR61C106KE15L C2012X5R0J106K SM0603 SM0805 PACKAGE SM0603 SM0603 SM0603 SM0603 SM0603 SM0603 SM0603 SM0603 SM0603 CASE-CC SM1206 SM0603
1000pF Multilayer Cap, 16V, 10% 0.01F Multilayer Cap, 16V, 10% 1F Multilayer Cap, 16V, 20%
0.15F Multilayer Cap, 16V, 10% 0.1F Multilayer Cap, 16V, 10%
2700pF Multilayer Cap, 16V, 10% 0.22F Multilayer Cap, 25V, 10% 56F 10F 100pF 330F Radial SP Series Cap, 25V, 20% Multilayer Cap, 25V, 20% Multilayer Cap, 16V, 10% SPCAP, 2V, 4M POLYMER CAP, 2.5V, 4.5M
1 30
C4 C40-C43, C47-C50, C53-C56, C59, C75, C78 C6 C82 C81, C83 L1 Q2 Q3, Q9 R10 R11 R16 R17, R18 R19 R26 R20, R40, R56 R30 R37 R38 R41 R42 R50
1000pF Multilayer Cap, 16V, 10% 10F Multilayer Cap, 6.3V, 20%
1 1 0 1 1 2 1 1 1 2 1 1 3 1 1 1 1 1 1
27pF
Multilayer Cap, 16V, 10%
GENERIC GENERIC
H1045-00270-16V10 H1045-00223-16V10
SM0603 SM0603
0.022F Multilayer Cap, 16V, 10% DNP 0.45H Inductor, Inductance 20%, DCR 7% N-Channel Power MOSFET N-Channel Power MOSFET 4.87k 4.22k 147k 10 1.91k 82.5 0 1.91k 1 11k 2.61k Thick Film Chip Resistor, 1% Thick Film Chip Resistor, 1% Thick Film Chip Resistor, 1% Thick Film Chip Resistor, 1% Thick Film Chip Resistor, 1% Thick Film Chip Resistor, 1% Thick Film Chip Resistor, 1% Thick Film Chip Resistor, 1% Thick Film Chip Resistor, 1% Thick Film Chip Resistor, 1% Thick Film Chip Resistor, 1%
NEC-TOKIN IR IR GENERIC GENERIC GENERIC GENERIC GENERIC GENERIC GENERIC GENERIC GENERIC GENERIC GENERIC PANASONIC GENERIC
MPCG1040LR45 IRF7821 IRF7832 H2511-04871-1/16W1 H2511-04221-1/16W1 H2511-01473-1/16W1 H2511-00100-1/16W1 H2511-01911-1/16W1 H2511-082R5-1/16W1 H2511-00R00-1/16W1 H2511-01911-1/16W1 H2511-01R00-1/16W1 H2511-01102-1/16W1 H2511-02611-1/16W1 ERT-J1VR103J H2511-03402-1/16W1
10mmx10mm PWRPAKSO8 PWRPAKSO8 SM0603 SM0603 SM0603 SM0603 SM0603 SM0603 SM0603 SM0603 SM0603 SM0603 SM0603 SM0603 SM0603
10k NTC Thermistor, 10k NTC 34k Thick Film Chip Resistor, 1%
27
FN6924.1 February 25, 2010
ISL62881, ISL62881B
CPU Application Reference Design Bill of Materials (Continued)
QTY REFERENCE 1 1 1 0 1 R6 R63 R7 R109, R110, R4, R8, R9 U6 VALUE 7.32k 3.65k 422k DNP IMVP-6.5 PWM Controller INTERSIL ISL62881HRTZ QFN-28 DESCRIPTION Thick Film Chip Resistor, 1% Thick Film Chip Resistor, 1% Thick Film Chip Resistor, 1% MANUFACTURER GENERIC GENERIC GENERIC PART NUMBER H2511-07321-1/16W1 H2511-03651-1/16W1 H2511-04223-1/16W1 PACKAGE SM0603 SM0805 SM0603
GPU Application Reference Design Bill of Materials
QTY REFERENCE VALUE 1 1 1 1 2 1 1 2 1 1 2 1 1 C11 C12 C13 C15 C16, C22 C18 C20 C17, C30 C21 C24 C27, C33 C3 C52 270pF 330pF DESCRIPTION Multilayer Cap, 16V, 10% Multilayer Cap, 16V, 10% MANUFACTURER GENERIC GENERIC GENERIC GENERIC GENERIC GENERIC GENERIC GENERIC GENERIC SANYO GENERIC GENERIC PANASONIC KEMET GENERIC MURATA TDK 15pF Multilayer Cap, 16V, 10% GENERIC GENERIC PART NUMBER H1045-00271-16V10 H1045-00331-16V10 H1045-00102-16V10 H1045-00103-16V10 H1045-00105-16V20 H1045-00154-16V10 H1045-00104-16V10 H1045-00224-25V10 H1045-00392-16V10 25SP56M H1065-00106-25V20 H1045-00101-16V10 EEXSX0D471E4 T520V477M2R5A(1)E4R5-6666 H1045-00102-16V10 GRM21BR61C106KE15L C2012X5R0J106K H1045-00150-16V10 H1045-00563-16V10 SM0603 SM0603 SM0603 SM0805 PACKAGE SM0603 SM0603 SM0603 SM0603 SM0603 SM0603 SM0603 SM0603 SM0603 CASE-CC SM1206 SM0603
1000pF Multilayer Cap, 16V, 10% 0.01F Multilayer Cap, 16V, 10% 1F Multilayer Cap, 16V, 20%
0.15F Multilayer Cap, 16V, 10% 0.1F Multilayer Cap, 16V, 10%
0.22F Multilayer Cap, 25V, 10% 3900pF Multilayer Cap, 16V, 10% 56F 10F 100pF 470F Radial SP Series Cap, 25V, 20% Multilayer Cap, 25V, 20% Multilayer Cap, 16V, 10% SPCAP, 2V, 4M POLYMER CAP, 2.5V, 4.5M
1 8
C4 C40, C41, C54-C56, C59-C61 C6 C82 C81, C83 L1 Q2 Q3, Q9 R10 R11 R16 R17, R18 R19 R26
1000pF Multilayer Cap, 16V, 10% 10F Multilayer Cap, 6.3V, 20%
1 1 0 1 1 2 1 1 1 2 1 1
0.056F Multilayer Cap, 16V, 10% DNP 0.88H Inductor, Inductance 20%, DCR 7% N-Channel Power MOSFET N-Channel Power MOSFET 2.37k 6.98k 47.5k 10 1.91k 82.5 Thick Film Chip Resistor, 1% Thick Film Chip Resistor, 1% Thick Film Chip Resistor, 1% Thick Film Chip Resistor, 1% Thick Film Chip Resistor, 1% Thick Film Chip Resistor, 1%
NEC-TOKIN IR IR GENERIC GENERIC GENERIC GENERIC GENERIC GENERIC
MPC1040LR88 IRF7821 IRF7832 H2511-02371-1/16W1 H2511-06981-1/16W1 H2511-04752-1/16W1 H2511-00100-1/16W1 H2511-01911-1/16W1 H2511-082R5-1/16W1
10mmx10mm PWRPAKSO8 PWRPAKSO8 SM0603 SM0603 SM0603 SM0603 SM0603 SM0603
28
FN6924.1 February 25, 2010
ISL62881, ISL62881B
GPU Application Reference Design Bill of Materials (Continued)
QTY REFERENCE VALUE 3 1 1 1 1 1 1 1 1 1 0 1 R20, R40, R56 R30 R37 R38 R41 R42 R50 R6 R63 R7 R109, R110, R4, R8, R9 U6 0 3.01k 1 11k 2.61k DESCRIPTION Thick Film Chip Resistor, 1% Thick Film Chip Resistor, 1% Thick Film Chip Resistor, 1% Thick Film Chip Resistor, 1% Thick Film Chip Resistor, 1% MANUFACTURER GENERIC GENERIC GENERIC GENERIC GENERIC PANASONIC GENERIC GENERIC GENERIC GENERIC PART NUMBER H2511-00R00-1/16W1 H2511-03011-1/16W1 H2511-01R00-1/16W1 H2511-01102-1/16W1 H2511-02611-1/16W1 ERT-J1VR103J H2511-02262-1/16W1 H2511-01002-1/16W1 H2511-03651-1/16W1 H2511-04123-1/16W1 PACKAGE SM0603 SM0603 SM0603 SM0603 SM0603 SM0603 SM0603 SM0603 SM0805 SM0603
10k NTC Thermistor, 10k NTC 22.6k 10k 3.65k 412k DNP IMVP-6.5 PWM Controller Thick Film Chip Resistor, 1% Thick Film Chip Resistor, 1% Thick Film Chip Resistor, 1% Thick Film Chip Resistor, 1%
INTERSIL
ISL62881HRTZ
QFN-28
29
FN6924.1 February 25, 2010
ISL62881, ISL62881B
Typical Performance
90 88 EFFICIENCY (%) 84 82 80 78 76 74 72 70 0 2 4 6 8 10 12 14 IOUT (A) 16 18 20 22 VIN = 12V VIN = 8V VIN = 19V EFFICIENCY (%) 86 88 86 84 82 80 78 76 74 72 70 0.1 1.0 IOUT (A) 10.0 VIN = 12V VIN = 8V VIN = 19V
FIGURE 27. CPU APPLICATION CCM EFFICIENCY, VID = 0.9V, VIN1 = 8V, VIN2 = 12.6V AND VIN3 = 19V
FIGURE 28. CPU APPLICATION DCM EFFICIENCY, VID = 0.9V, VIN1 = 8V, VIN2 = 12.6V AND VIN3 = 19V
0.91 0.90 0.89 0.88 VOUT (V) 0.87 0.86 0.85 0.84 0.83 0.82 0.81 0.80 0 2
VIN = 19V
VIN = 12V VIN = 8V 4 6 8 10 12 14 IOUT (A) 16 18 20 22
FIGURE 29. CPU APPLICATION CCM LOAD LINE, VID = 0.9V, VIN1 = 8V, VIN2 = 12.6V AND VIN3 = 19V
FIGURE 30. CPU MODE CLK_EN# DELAY, VIN = 19V, IO = 0A, VID = 1.2V, Ch1: PHASE1, Ch2: VO, Ch4: CLK_EN#
FIGURE 31. CPU MODE SOFT-START, VIN = 19V, IO = 0A, VID = 1.2V, Ch1: PHASE, Ch2: VO
FIGURE 32. GPU MODE SOFT-START, VIN = 19V, IO = 0A, VID = 1.2V, Ch1: PHASE, Ch2: VO
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FN6924.1 February 25, 2010
ISL62881, ISL62881B
Typical Performance (Continued)
FIGURE 33. CPU MODE SHUT DOWN, VIN = 19V, IO = 0A, VID = 1.2V, Ch1: PHASE, Ch2: VO
FIGURE 34. GPU MODE SHUT DOWN, VIN = 19V, IO = 0A, VID = 1.2V, Ch1: PHASE, Ch2: VO
FIGURE 35. CCM STEADY STATE, CPU MODE, VIN = 8V, IO = 1A, VID = 1.2375V, Ch1: PHASE, Ch2: VO
FIGURE 36. DCM STEADY STATE, CPU MODE, VIN = 12V, IO = 1A, VID = 1.075V, Ch1: PHASE1, Ch2: VO, Ch3: COMP, Ch4: LGATE
1000 900 IMON-VSSSENSE (mV) 800 700 600 500 400 300 200 100 0 0 2 4 6 TARGET 8 10 12 IOUT (A) 14 16 18 20 22 IMON
Phase Margin
Gain
FIGURE 37. GPU MODE REFERENCE DESIGN LOOP GAIN T2(s) MEASUREMENT RESULT
FIGURE 38. IMON, VID = 1.2375
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FN6924.1 February 25, 2010
ISL62881, ISL62881B
Typical Performance (Continued)
FIGURE 39. LOAD TRANSIENT RESPONSE WITH OVERSHOOT REDUCTION FUNCTION DISABLED, GPU MODE, VIN = 12V, VID = 0.9V, IO = 12A/22A, di/dt = "FASTEST"
FIGURE 40. LOAD TRANSIENT RESPONSE WITH OVERSHOOT REDUCTION FUNCTION DISABLED, GPU MODE, VIN = 12V, VID = 0.9V, IO = 12A/22A, di/dt = "FASTEST"
FIGURE 41. LOAD TRANSIENT RESPONSE WITH OVERSHOOT REDUCTION FUNCTION DISABLED, GPU MODE, VIN = 12V, VID = 0.9V, IO = 12A/22A, di/dt = "FASTEST"
FIGURE 42. LOAD TRANSIENT RESPONSE WITH OVERSHOOT REDUCTION FUNCTION DISABLED, GPU MODE, VIN = 12V, VID = 0.9V, IO = 12A/22A, di/dt = "FASTEST"
FIGURE 43. CPU MODE VID TRANSITION, DPRSLPVR = 0, IO = 2A, VID = 1.2375V/1.0375V, Ch2: VO, Ch3: VID4
FIGURE 44. GPU MODE VID TRANSITION, DPRSLPVR = 0, IO = 2A, VID = 1.2375V/1.0375V, Ch2: VO, Ch3: VID4
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FN6924.1 February 25, 2010
ISL62881, ISL62881B
Typical Performance (Continued)
FIGURE 45. CPU MODE VID TRANSITION, DPRSLPVR = 1, IO = 2A, VID = 1.2375V/1.0375V, Ch2: VO, Ch3: VID4
FIGURE 46. GPU MODE VID TRANSITION, DPRSLPVR = 1, IO = 2A, VID = 1.2375V/1.0375V, Ch2: VO, Ch3: VID4
For additional products, see www.intersil.com/product_tree Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 33
FN6924.1 February 25, 2010
ISL62881, ISL62881B
Package Outline Drawing
L28.4x4
28 LEAD THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 0, 9/06
4 . 00 PIN 1 INDEX AREA A 2 . 50 B 0 . 40 22 21 28 PIN #1 INDEX AREA CHAMFER 0 . 400 X 45
1 0 . 4 x 6 = 2.40 REF
4 . 00
2 . 50
0 . 40
15 0 . 10 2X 14 8
7
0 . 20 0 . 05
TOP VIEW
0 . 4 x 6 = 2 . 40 REF 3 . 20
0 . 10 M C A B
BOTTOM VIEW
SEE DETAIL X'' (3 . 20) PACKAGE BOUNDARY MAX. 0 . 80 SEATING PLANE (28X 0 . 20) 0 . 00 - 0 . 05 0 . 20 REF 0 . 08 C 0 . 10 C C
SIDE VIEW
(2 . 50) (3 . 20)
(0 . 40) C
0 . 20 REF
5
(0 . 40) (2 . 50) (28X 0 . 60)
0 ~ 0 . 05
DETAIL "X" TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Controlling dimensions are in mm. Dimensions in ( ) for reference only. 2. Unless otherwise specified, tolerance : Decimal 0.05 Angular 2 3. Dimensioning and tolerancing conform to AMSE Y14.5M-1994. 4. Bottom side Pin#1 ID is diepad chamfer as shown. 5. Tiebar shown (if present) is a non-functional feature.
34
FN6924.1 February 25, 2010
3 . 20
ISL62881, ISL62881B
Package Outline Drawing
L32.5x5E
32 LEAD THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 0, 03/09
3.50 5.00 A B 6 PIN 1 INDEX AREA 24 25 28X 0.50 32 1 6 PIN #1 INDEX AREA
5.00
3.50
3.70 Exp. DAP
17 (4X) 0.15 32X 0.25 4 0.10 M C A B 16 3.70 Exp. DAP 9
8
32X 0.40
TOP VIEW
SIDE VIEW
BOTTOM VIEW
SEE DETAIL "X" ( 4.80 ) ( 3.50) Max 0.80 ( 28X 0.50) 0.10 C SEATING PLANE 0.08 C C
SIDE VIEW
( 4.80 ) (3.70 ) ( 3.50)
(32X 0.25)
C
0 . 2 REF
5
( 32 X 0.60)
0 . 00 MIN. 0 . 05 MAX.
TYPICAL RECOMMENDED LAND PATTERN
DETAIL "X"
NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal 0.05 4. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature.
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FN6924.1 February 25, 2010

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